The present invention relates to a data output circuit for a dynamic memory device with a nibble mode function.
For large capacity semiconductor memory devices, dynamic memory devices are mainly used because the use of such memory devices requires fewer transistors for making a memory cell. Some of the dynamic memories, particularly large capacity memories, for example, 256 Kilo bits, have a nibble mode function in order to speed up the read-out and write operation. The 256 Kilo bits memory device with the nibble mode function is constructed as shown in FIG. 1, to have four memory cell groups Ca-Cd each consisting of 64 Kilo bits. The memory cells of 64 Kilo bits in each of the cell groups Ca-Cd are selectively accessed by 8-bit row addresses A.sub.0R -A.sub.7R and 8-bit column addresses A.sub.0C -A.sub.7C.
In a read out mode of the nibble mode, a ROW ADDRESS STROBE (RAS) and a COLUMN ADDRESS STROBE (CAS) cooperate to specify addresses (x, y) of the memory cell groups Ca-Cd. The contents in the memory cells located at the specified addresses are read out and latched in a latch section, or a 4-bit latch Lh. Subsequently, every time the logical value of the CAS is changed, the contents of the 4-bit latch Lh are sequentially and cyclically read out through a read register Rr. The read out data is produced as output data Dout. Then, every time a logical value of the CAS is changed, and input data Din are sequentially loaded into the bit stages of the 4-bit latch Lh, through a write register Wr, the data are written into memory cells located at the specified addresses of those cell groups Ca-Cd. In FIG. 1, a program counter Pc specifies one specific bit in the 4-bit latch Lh. While receiving the most signigicant bit (MSB) A.sub.8R of the row address signal and the MSB A.sub.8C of the column address signal, the program counter Pc cyclically performs the counting operation according to a change of the logical value of the CAS. By the count of the program counter Pc, one specific bit is selected from those in the 4-bit latch counter Lh. A selector Sr selects either the read out register Rr or the write register Wr according to an operation mode of the semiconductor memory device, either a read mode or a write mode.
FIG. 2 shows timing diagrams illustrating a read cycle of the semiconductor memory device. A row address is given by an address signal A0-A8, applied during an effective period to indicate that the RAS is low or L in logical level. A column address is given by an address signal A0-A8, applied during an effective period to indicate that the CAS is L. The row and column addresses are selected by these signals. Then, every time the CAS changes in logical level, the contents in the bit stages of the 4-bit latch Lk are sequentially and cyclically read out from the memory cells of the semiconductor memory device. In the read operation, the memory cell, as specified by the row address A.sub.8R and the column address A.sub.8C, is first read out.
A write mode of the semiconductor memory device is executed according to timing diagrams shown in FIG. 3. A row address is given by an address signal A0-A8, as applied during an effective period, to indicate that the RAS is L. A column address is given by an address signal A0-A8, as applied during an affective period to indicate that the CAS is L. After a row address and a column address are selected by these signals, a write signal (WRITE) is effected and the write operation is performed every time the signal CAS changes.
Let us consider the case when the 4-bit latch Lh contains c, d, a, and b, for example, data e-o are sequentially written into the memory cells. In this case, the data c is first replaced by data e. Subsequently, the data is replaced from d to f, a to g, b to h, e to i, f to j, g to k, b to h, i to m, j to n and k to o. The finally replaced data is written into the memory cell in each of the cell groups Ca-Cd as specified by the row address signal and the column address signal, and the data already stored is discarded. Therefore, the contents of the memory cells in the cell groups Ca-Cd, corresponding to the cells a-d in the 4-bit latch Lh, are o, l, m, and n, respectively.
As described above, in the dynamic memory device with such a nibble mode function, by changing the CAS at short periods while keeping the RAS at L, it can read out or write the contents of the 4-bit latch Lh at a high speed in synchronism with the CAS, without changing the address.
FIG. 4 shows a circuit diagram illustrating an arrangement of one bit stage of the conventional 4-bit latch Lh. As shown, latch line pairs I/O and I/O are respectively connected to paired output lines DO and DO through series circuits containing MOSFETs 1-4 and 5-8. The gates of the MOSFETs 1 and 2 are wired together and to the latch line I/O. Likewise, the gates of the MOSFETs 5 and 6 are wired together and to the latch line I/O. A series connection point of the MOSFETs 1 and 2 and a series connection point of the MOSFETs 5 and 6 are interconnected through a node N1. The node N1 is connected through a MOSFET 9 to a power source V.sub.SS. A clock pulse .phi.L is applied to the gate of the MOSFET 9. The MOSFETs 2 and 3 are series connected to provide a node N2. The MOSFETs 6 and 7 are series connected to provide a node N3. The gates of MOSFETs 3 and 7 as a first transistor pair are wired together. A clock pulse .phi.g is applied to the interconnected gates of the first transistor pair. Further, the MOSFETs 3 and 4 are series connected to provide a node N4, and the MOSFETs 7 and 8 are series connected and provide a node N5. The gates of the MOSFETs 4 and 8 as a second transistor pair are connected together. A select signal R is applied to the interconnected gates of the second transistor pair. The read register Rr, succeeding the 4-bit latch register Lh thus arranged, contains a MOSFET 10, inserted between the output line pair DO and DO, and MOSFETs 11 and 12, inserted between the power sources V.sub.DD, with the MOSFET 10 interposing therebetween. A clock pulse .phi.p is applied to the gates of these MOSFETs 10-12.
In a write mode, a level on the latch line pair I/O and I/O is forced to be changed according to the write data. At this time, the clock .phi.g is placed in a L level to turn off the first transistor pair of the MOSFETs 3 and 7, in order that levels on the latch output line pair DO and DO remain unchanged.
Four latch circuits, each as shown in FIG. 4, are arranged in a parallel fashion to form the 4-bit latch Lh. Potentials on the latch output line pair DO and DO are produced through the next stage read register Rr.
With such an arrangement, the latch line pair I/O and I/O are precharged up to a potential of the power / source V.sub.DD when the RAS is H, as shown in a timing chart of FIG. 5. When the CAS is H, the clock .phi.p is Vp (&gt;V.sub.DD +V.sub.T), and hence the latch output line pair DO and DO are precharged up to V.sub.DD by a combination of the MOSFETs 10-12. When the CAS falls, data from the memory cell is transferred to the latch line pair I/O and I/O, so that the latch line pair has a logical level as given by the contents of the data transferred. In this logical state on the latch line pair I/O and I/O, the clock .phi.L rises and the node N1 is coupled with a power source V.sub.SS. The contents of the data cause one of the MOSFETs 1 and 5 constituting a flip-flop to turn on. At this time, the data causes one of the MOSFETs 2 and 6 to turn on. This results in simultaneous discharge from one of the latch line pair I/O and I/O and one of the nodes N2 and N3. The nodes N1-N3 are charged at a voltage V.sub.DD -V.sub.T at the precharging time where the RAS is H. Here, if the latch is selected, the clock pulse .phi.g rises up to a potential Vp, and slightly later a select signal R also rises. Accordingly, the nodes N2 and N4 are connected to the output line DO, while the nodes N3 and N5 are connected to the output line DO. Under this condition, one of the latch output lines DO and DO is discharged according to the data held by the flip-flop made up of the MOSFETs 1 and 5. At the same time, the other is in a floating state and keeps a precharge level.
Under this condition, one of the output lines DO and DO is connected to the power source V.sub.SS and its potential is reliably fixed at that potential. However, the other is in a floating state and if it is connected to another node, charges on this output line are shared with the node. The potential on the output line drops or is greatly changed by charge leakage or the like.
FIG. 6 shows a timing diagram exaggeratedly illustrating a read cycle in the nibble mode. As shown, valid data is output after a predetermined time t.sub.NCAC following the fall of the column address strobe signal CAS. The valid data terminates after a predetermined time t.sub.off following the rise of the column address strobe signal CAS. These time delays t.sub.NCAC and t.sub.off are determined by the associated circuit. A cycle time t.sub.NC can be set at a proper value if it is larger than a minimum value t.sub.NCmin, which depends on minimum values t.sub.NCPmin, of a precharge time t.sub.NCP and t.sub.NCASmin, of a pulse width t.sub.NCAS of the column address strobe signal CAS for guaranteeing circuit operation.
In receiving data, a valid data period of the output data Dout is important, that is, a width of a data window. A memory device with a large data window is very easy to use because the design on the data transfer between the memory device and the peripheral circuit suffers from fewer design restrictions. To widen the data window, it is sufficient to enlarge the pulse width t.sub.NCAS of the column address strobe signal CAS. This results in an elongation of the cycle time t.sub.NC. The elongated cycle time t.sub.NC degrades the high speed performance as a useful feature of the nibble mode function. Ideally, it is desired that a maximum data window be gained within a minimum cycle time.
Theoretically, the period of the data window can be enlarged up to the cycle time t.sub.NC, if desired. In this case, however, there is a limit in reducing the time period t.sub.NCAC ranging from the fall of the column address strobe signal CAS to the data output. Further, a reduction of the time t.sub.off, if done, can be at most approximately the minimum value t.sub.NCPmin of the precharge period. Therefore, a practical maximum value of the data window is approximately t.sub.NCAS -t.sub.NCAC +t.sub.NCPmin. This indicates that when the memory device is operated with the minimum cycle time t.sub.NCmin, the data window is approximately t.sub.NCmin -t.sub.NCAC and is very small.
Another way to enlarge the data window is to further elongate the time t.sub.off. The clock pulse used in the precharging system is used for resetting the data output circuit. Therefore, if the time t.sub.off is set at large value, the reset clock pulse must be greatly delayed behind the rise of the column address strobe signal CAS. If an extremely short precharge time t.sub.NCP is set, the reset clock pulse fails to rise, and the read operation enters into the next read cycle. To avoid this, it is necessary increase the minimum value t.sub.NCPmin during the precharge period. The result is an enlargement of the minimum value t.sub.NCmin of the cycle time and a degradation of the high speed performance associated with the nibble mode function.
Turning now to FIG. 7, there is shown a circuit diagram of the data output section of the read register Rr. As shown, three MOSFETs 11-12, connected in series fashion, are connected at both ends to the power source V.sub.DD. The series connection points of these MOSFETs are respectively coupled with paired output lines DO and DO of the latch circuit. The paired output lines DO and DO are respectively connected through the MOSFETs 13 and 14 to the power source V.sub.SS. Further, those output lines are respectively connected to the gates of the MOSFETs 17 and 18, through the MOSFETs 15 and 16 and nodes N6 and N7. A precharge clock .phi.p is applied to the MOSFETs 10-12. The gates of the MOSFETs 15 and 16 are connected together to the power source V.sub.DD. Drive signals .phi.out are respectively connected to the power supply V.sub.SS through the series paths of the MOSFETs 17 and 19 and of the MOSFETs 18 and 20. The gate of the MOSFET 13 is connected to the power source V.sub.SS through the node N8 and the MOSFET 21. A precharge clock .phi.p is applied to the gate of the MOSFET 21. The gate of the MOSFET 13 is connected to the gates of the MOSFETs 20 and 22 and to a series connection point of the MOSFETs 17 and 19. The gate of the MOSFET 14 is connected to the power source V.sub.SS through the MOSFET 23, of which the gate is impressed with a precharge clock pulse .phi.p. The gate of the MOSFET 14 is connected to the gates of the MOSFETs 19 and 24 and a series connection point of the MOSFETs 18 and 20. The MOSFETs 24 and 22 as respectively the load transistor and the drive transistor are connected in series between the power sources V.sub.DD and V.sub.SS. Output data is derived from a data output node Output, or a series connection point of these transistors 24 and 22.
The read register Rr with such a circuit arrangement operates in a sequence as shown in FIG. 8 As shown, at the precharge time or when the column address strobe signal CAS is H, the precharge clock .phi.p is Vp (&gt;V.sub.DD +V.sub.T), and the paired output lines DO and DO in the latch circuit are at V.sub.DD level. A potential at the node N6 between the MOSFETs 15 and 17 is V.sub.DD -V.sub.T. A potential at the node N7 between the MOSFETs 16 and 18 is also V.sub.DD -V.sub.T. Also at this time, the node N8, associated with the gate of the MOSFET 22, and the node N9, associated with the MOSFET 24, are at potential of V.sub.SS. Under this condition, the MOSFETs 22 and 24 are turned off and the output node Output of the read register is at a high impedance.
When the column address strobe signal CAS is L, the precharge clock signal .phi.p is also L. At this time, if data is applied to the register Rr through the output line pair DO and DO, the nodes N6 and N7 are placed at the potential according to the applied data. When the output clock .phi.out rises up to Vp, the nodes N8 and N9 are at Vp level according to the data. Potentials at the nodes N8 and N9 are fed back to the output line pair DO and DO, through the MOSFETs 13 and 14, thereby ensuring the data transfer. According to the potentials on the nodes N8 and N9, one of the MOSFETs 22 and 24 is turned on and the output node Output is at V.sub.DD or V.sub.SS. When the column address strobe signal CAS rises, the precharge clock .phi.p rises too. The nodes N8 and N9 are both at V.sub.SS, and the output node Output is at a high impedance. In this case, to make the time t.sub.off long, it is sufficient to delay the rise of the precharge clock .phi.p. When the rise of the precharge clock .phi.p is delayed too much, it can not rise within the precharge cycle of the column address strobe signal CAS, as indicated by .phi.R' in FIG. 8. Further, the output line pair DO and DO of the latch circuit are not precharged. As a result, it is impossible to transfer data in the succeeding fall cycle of the column address strobe signal CAS. Therefore, the delay of the time t.sub.off is limited within the time period allowing the precharge clock .phi.p to rise. This implies that the elongation of the time t.sub.off must be approximately within the minimum value t.sub.NCPmin of the precharge time period. For this reason, an insufficient width of the data window can be obtained.